This invention relates to an information processing system which is applicable to a super computer or the like.
Information processing systems, such as a super computers are used to solve a complex problems which require a large scale or amount of scientific and technical calculation. For this purpose, a plurality of processors are included in the information processing system in addition to a main memory device so as to concurrently execute or process jobs. Such concurrent processing enables high speed calculation. The processors may comprise a central processing unit (CPU), a plurality of arithmetic processing units, and an input/output processing unit.
It is a recent trend that such problems are becoming more complicated and require very large scale calculations. Such large scale calculations makes it difficult to store all data for the complex calculations in the main memory device. Under the circumstances, an extended buffer memory of a large memory capacity is usually used in the information processing system to store the data. Therefore, an extended memory data transfer operation is carried out between the main memory device and the extended buffer memory in response to a transfer request which is issued from a selected one of the processors and which may be called an extended memory transfer request. During such an extended memory data transfer operation, the extended buffer memory must be locked so as to avoid collision among extended buffer memory transfer requests issued from the other processors. Such a lock operation will be referred to as a communication lock operation.
It is to be noted that lock information is stored in the main memory device and is accessed by each processor on carrying out the communication lock operation.
In the meanwhile, each of the arithmetic processing units may execute a vector instruction which requires a main memory data transfer operation of vector data to the main memory device to store the data into the main memory. In addition, another main memory data transfer operation may be carried out between the main memory device and the input/output processor. During PG,4 such main memory data transfer operations between the main memory device and each arithmetic processing unit and between the main memory device and the input/output processor, the main memory device can not be used by the other processors. This shows that the main memory device is not always available to the processors when the extended memory data transfer request is issued to carry out the extended memory data transfer operation between the main memory device and the extended buffer memory. In other words, the main memory device is often in a busy state.
The extended memory data transfer request might be issued from one of the processors during the busy state of the main memory device. In this event, the extended memory data transfer request is inevitably halted without execution until the busy state is released in the main memory device. This shows that the lock information can be neither read out of the main memory device nor released to put the extended buffer memory into an unlocked state until the main memory device is released after completion of the main memory data transfer operation. This gives rise to a reduction of throughput of the information processing system.
U.S. patent application Ser. No. 290,623 filed Dec. 24, 1987, by Akira Jippo and assigned to the present assignee, proposed an information processing system which comprises a central processing unit (CPU), a plurality of arithmetic processors, an input/output processor, and a system controller and which can deal with transfer requests simultaneously produced from the CPU, the arithmetic processors, and the input/output processor. To this end, a transfer controlling arrangement is included in the system controller. However, no consideration is made about processing carried out when the main memory device is put into a busy state.